Its more the geometry of the process than the rate of failure. The post is just saying, "if the rate were constant". Basically, throw a dart at a wafer. Wherever the dart hits, the whole circuit/chip containing that point is now worthless. Assuming you threw the same number of darts (failures) at a board with a smaller chip, and a board with a large chip, the larger process wafer loses more total silicon (as a percentage of usable area).
With smaller chips, you have a smaller "grid" for your dart to land on. So the total number of failures (darts) being the same, you still end up with less usable silicon, since the bigger grid means you throw away a lot more surface area with a failure.
The point is that the amount of silicon that is wasted when there is a defect is amplified more with larger chips. That assumption was more for ease of explanation, but perhaps I could have explained better.
With smaller chips, you have a smaller "grid" for your dart to land on. So the total number of failures (darts) being the same, you still end up with less usable silicon, since the bigger grid means you throw away a lot more surface area with a failure.
Take a look at this picture of a failure map, if you would like some visuals: https://ars.els-cdn.com/content/image/1-s2.0-S09521976120008...