[tonmoy]

A thief would be using the RTL to make a clone of NVIDIA graphics card, they’d be using the IP cores as modules in their own designs. With some minor adjustment it shouldn’t be too difficult to get at least most of the RTL working in a different mode (maybe lower clock speed)

[ChuckNorris89]

That's not how VLSI chip design works. You can't just take the RTL designed for 5 - 8 nm, zoom it up to 65nm and expect it to still work.

When you design a CPU or GPU, the RTL, like the core pipelines, schedulers, and various buses, are designed from the start on a certain manufacturing process where they're expected to work correctly at specific frequencies that are fast enough to feed the pipelines at the right timings, in order to get the top expected performance. Failure to meet the fabrication process expectations means the RTL design will perform much worse than expected in practice.

That's why many of Intel's past designs sucked so bad in the performance and efficiency category as their 10nm manufacturing process fell behind, so they had to scale their newer designs back on the aging 14+++++ process, which caused those CPUs to flop big time.

[ginko]

>maybe lower clock speed

That is an understatement. 65nm is ten times larger than what NVidia is currently using. That means the area would be 100 times larger and any signal distances 10 times larger. And keep in mind that NVidia GPU designs already take up quite a bit of area on modern nodes.

So you'd likely have to cut it down to a 100th of modules which would run at 10th speed.

[thfuran]

Is signal propagation actually close to being a limiting factor in clock speeds for most designs? I thought it's pretty much always thermals.

[gorkish]

That is not the point; the signal propagation times in the VLSI blocks are engineered to work properly at the specific physical size. If the structures are scaled to a larger node size, the timing variances increase. If you want to do this, you can either 1) reengineer all the VLSI blocks to meet timing requirements at the larger node size (maybe impossible) or 2) slow the clock speed to loosen the requirements.

[thfuran]

Isn't it exactly the point? If, provided sufficient cooling, you could double the clock speed without running into clock skew or other timing issues, then timing issues shouldn't be a problem if you want to scale things up physically by 50% without touching the clocks. I don't think you'd have to lower clocks by 90% to increase size of most designs tenfold. Or rather, that the reason you'd have to if you did wouldn't be due to signal propagation time.