[gorkish]

That is not the point; the signal propagation times in the VLSI blocks are engineered to work properly at the specific physical size. If the structures are scaled to a larger node size, the timing variances increase. If you want to do this, you can either 1) reengineer all the VLSI blocks to meet timing requirements at the larger node size (maybe impossible) or 2) slow the clock speed to loosen the requirements.

[thfuran]

Isn't it exactly the point? If, provided sufficient cooling, you could double the clock speed without running into clock skew or other timing issues, then timing issues shouldn't be a problem if you want to scale things up physically by 50% without touching the clocks. I don't think you'd have to lower clocks by 90% to increase size of most designs tenfold. Or rather, that the reason you'd have to if you did wouldn't be due to signal propagation time.