I get that, but the link literally says: "The Open Source FPGA ASIC". With that in the title, I would expect to be able to find the source of the FPGA.
Looks like this has been put together by Efabless themselves. I dont think the rtl would be too different from OpenFPGA(https://github.com/lnis-uofu/OpenFPGA) married to the caravel f/w.
My guess would be that the first prototype that they made was too buggy to publish. The promise is that they will share the final design, and I am fine with that.
(I am not affiliated with the project, but backed it)
Yikes. If I'm understanding that correctly every chip that came back from MPW-1 was more or less unusable - they were all required to gate access to I/Os behind the same management processor provided by the company organising the run, and because that management processor was broken they couldn't configure the I/Os to route through to their own designs.
