I thought AMD had already brought chiplets to data center CPUs a long time ago [1], [2] and that is why they are leading currently, now that they have multiple generations of chiplet data center CPUs out? [3]
Yes. The article (second paragraph) clearly states that this is a first for Intel, not for Data Centers.
Given that this is a trade-ish publication, I think writers/editors will more or less assume their audience understands the smackdown that AMD has been laying on Intel and AMD's chiplet strategy.
Though it's not even really a first for Intel. They made the Xeon 9200 series two years ago, and while those were slapdash and hard to buy, it's hard to argue that they don't deserve this crown. Two dies in a single package, each with 28 cores and memory controllers and I/O.
Even when Intel moves to heterogeneous dies, that won't actually be a first for them, even in the modern era. Several early i3/i5/i7 models had one die with two cores and another die that handled memory and I/O.
You are right AMD has done that. I don't know if it is the reason they are leading -- they have better process technology and in many ways better core design as well.
But this story is about Intel. Though it depends on how you define "chiplet". In this article it looks like 4 identical chips wired on a package each with their own IO and memory controllers. That's very different from from AMD's core chips wired to an IO chip, and is nothing new for Intel. https://en.wikipedia.org/wiki/Multi-chip_module
It's the expected response from Intel when they are unable to compete on throughput per socket with a single chip (they went to DCMs during the period of Opteron dominance too). I don't know what the story is really -- they said the latency was too high to do this before but they've already done something effectively the same (and multi socket SMP systems have even higher chip to chip latency again, so clearly it can be done). I guess they just improved the on package interconnect performance a bit, but almost certainly they would have done a multi chip to compete with AMD even if they were not able to improve that latency.
Sapphire Rapids is more similar to AMD's "Naples" Epyc from 2017 which also used four identical dies. Intel's mesh and EMIB should give Sapphire Rapids dramatically more internal bandwidth than AMD designs. It counts as chiplets IMO because the dies aren't intended to be used standalone.
More similar to that than? The current AMD chip+io die approach? Sure.
As I said, "chiplet" just depends on a definition, there is really no good single one. Almost certainly the dies could be used standalone, and it wouldn't be surprising if some were for low end SKUs (modulo the statement in the article that they won't for this generation) -- there are some mesh IOs on some length about 1/2 the die on two edges, that's it. Not much area.
also done to allow more SKUs from the same components, allowing AMD to make up any mix of 8 to 64 core chips without manufacturing fixed quantities of each or disabling most of the die (expensive)
There's some truth to this in the sense that a single die would almost always have better performance than chiplets, but chiplets also reduce cost and they make larger core counts possible. A single die literally can't fit more than ~48 big cores with the associated cache and I/O, so 56, 64, or 96-core processors are only possible using chiplets.
That was indeed my point - you said it perfectly. I meant, that there is nothing for the customer in chiplets except cost.
Intel went the EMIB route to route through embedded silicon but people need to be reminded on HN that chiplet/fabric architecture is not something to brag about as a feature - which is what a lot of comments are doing (AMD did it first!). Intel went through this mess because they had to due to yield. It ain't a feature for the customer.
Given that this is a trade-ish publication, I think writers/editors will more or less assume their audience understands the smackdown that AMD has been laying on Intel and AMD's chiplet strategy.