[throwawaylinux]

You are right AMD has done that. I don't know if it is the reason they are leading -- they have better process technology and in many ways better core design as well.

But this story is about Intel. Though it depends on how you define "chiplet". In this article it looks like 4 identical chips wired on a package each with their own IO and memory controllers. That's very different from from AMD's core chips wired to an IO chip, and is nothing new for Intel. https://en.wikipedia.org/wiki/Multi-chip_module

It's the expected response from Intel when they are unable to compete on throughput per socket with a single chip (they went to DCMs during the period of Opteron dominance too). I don't know what the story is really -- they said the latency was too high to do this before but they've already done something effectively the same (and multi socket SMP systems have even higher chip to chip latency again, so clearly it can be done). I guess they just improved the on package interconnect performance a bit, but almost certainly they would have done a multi chip to compete with AMD even if they were not able to improve that latency.

[wmf]

Sapphire Rapids is more similar to AMD's "Naples" Epyc from 2017 which also used four identical dies. Intel's mesh and EMIB should give Sapphire Rapids dramatically more internal bandwidth than AMD designs. It counts as chiplets IMO because the dies aren't intended to be used standalone.

[throwawaylinux]

More similar to that than? The current AMD chip+io die approach? Sure.

As I said, "chiplet" just depends on a definition, there is really no good single one. Almost certainly the dies could be used standalone, and it wouldn't be surprising if some were for low end SKUs (modulo the statement in the article that they won't for this generation) -- there are some mesh IOs on some length about 1/2 the die on two edges, that's it. Not much area.