[OJFord]

I like the sound of that, but my verilog's rusty, a suggestion for the readme: show what the equivalent verilog would be for the example, or better I suppose the actual verilog that it would transpile to.

I suppose your target audience is mainly more familiar with verilog (though not necessarily I suppose - could have only ever used VHDL) but I'm interested in playing with it, just haven't used verilog, or FPGAs at all, since university.

[ithkuil]

Take a look at the examples dir on github: https://github.com/nickmqb/wyre/tree/master/examples

Then look at the "output" subdirectory and you'll find a verilog generated file for each example of the parent directory.