(Disclosure: I wrote the simulation engine behind CircuitLab, a mixed-mode [i.e. analog+digital combined] circuit simulation engine.)
Writing software to do digital logic simulation is quite simple. Everything is event-driven: if a signal "A" changes from 0->1 at time t_0, and this signal is an input to some gate "X", then at time t_0 + t_p (propagation delay) the output of that gate will update with the new value, as defined by that particular gate/register/whatever. So events can originate from (1) external signals (such as buttons/switches), (2) clocks, (3) the output of an earlier gate updating its output after a propagation delay. You can then just propagate changes throughout the digital circuit, looking at what's connected to the signal that just changed state.
It gets a bit more tricky once you combine analog and digital simulations simultaneously. :)
Real digital logic is usually clocked at a rate which is slow enough for propagation and other effects to settle AND/OR for chip design, parts are speed binned after manufacture.
The principle is the same - you drop the clock rate until the circuit works reliably. You can usually do some ballpark estimates while designing - e.g. a small board full of TTL will usually be happy clocked at 10% of the theoretical maximum, it may work at 25%, 50% is optimistic unless the circuit is trivial, and 100% is only possible for a single gate or two if the board design is also fast enough.
Occasionally you'll see non-clocked designs, but they're much harder to model at speed because everything turns into a monostable, and each monostable will have a time tolerance. This is a bad thing from a design and reliability POV.
It's the same principle at the pro level, with the difference that you have multi-layer boards and much faster clock rates. The board routing uses some tricks to minimise propagation, switching transients, and transmission line reflections, but mostly there's incredibly advanced engineering and modelling involved in making a small-ish board that works reliably at GHz rates - certainly more complex than trying to guesstimate propagation using a very simple delay model.
Thank you for your answer. Since non-clocked designs are hard to
model and clocked designs at high rates are also hard to model, is
there ever a crossover point in hardness (e.g., when they exceed a
a certain number of components or physical size) or are clocked designs always considered asymptotically easier? On a related note, does the competitive advantage of one hardware manufacturer over another reduce primarily to a matter of which one has better circuit simulation and routing software?
I have just a basic understanding but for example in a serial to digital converter they will use a base clock and a phase delayed clock signals to capture multiple samples in one base clock cycle time instead of just cranking up the base clock frequency.
Writing software to do digital logic simulation is quite simple. Everything is event-driven: if a signal "A" changes from 0->1 at time t_0, and this signal is an input to some gate "X", then at time t_0 + t_p (propagation delay) the output of that gate will update with the new value, as defined by that particular gate/register/whatever. So events can originate from (1) external signals (such as buttons/switches), (2) clocks, (3) the output of an earlier gate updating its output after a propagation delay. You can then just propagate changes throughout the digital circuit, looking at what's connected to the signal that just changed state.
It gets a bit more tricky once you combine analog and digital simulations simultaneously. :)