[gradschool]

Thank you for your answer. Since non-clocked designs are hard to model and clocked designs at high rates are also hard to model, is there ever a crossover point in hardness (e.g., when they exceed a a certain number of components or physical size) or are clocked designs always considered asymptotically easier? On a related note, does the competitive advantage of one hardware manufacturer over another reduce primarily to a matter of which one has better circuit simulation and routing software?

[pkaye]

I have just a basic understanding but for example in a serial to digital converter they will use a base clock and a phase delayed clock signals to capture multiple samples in one base clock cycle time instead of just cranking up the base clock frequency.