[lnsru]

I am curious, why System Verilog isn’t mentioned in this article. It is much much better than Verilog and is used in industrial applications.

What I am missing are 2 topics: timing analysis and debugging. Static timing analysis and proper timing constrains are crucial for functional design. No tool can differentiate without constrains a slow signal signal toggling LED every 10 seconds from DDR3 533 MHz differential clock line.

Debugging FPGAS design cannot be avoided. Even if design works in simulator, it fails very often on real hardware. And then real fun starts. Xilinx has Integrates Logic Analyzer, Intel has Chipscope. Other vendors have their own similar tools. There are best FPGA designer’s friends. But these tools can’t be trusted, they break sometimes design in unexpected ways. Designer must develop gut feeling, what’s happening. Synthesis of design with integrated logic analyzer takes much more time than regular one. Debugging cycles are insane long. Forgetting one signal can mean 2 hours waiting, so add them all at very beginning.

Writing hardware description language is easy part. As somebody already mentioned, everybody can count ones and zeros. First problem every software engineer encounters is simple: there is nothing to program. FPGA design is about describing your system with these ancient language. Second problem is using bulky toolchain. It’s more than compile and debug buttons. In fact, there is huge machine processing code to bitstream. And it’s complexity naturally takes time to understand, you don’t need to be smart to be FPGA designer.

[q3k]

> I am curious, why System Verilog isn’t mentioned in this article. It is much much better than Verilog and is used in industrial applications.

Probably because it has very limited support in open source tooling, same as VHDL.

[orbifold]

That is not true: Verilator is an excellent tool that compiles a large subset of synthesizable System Verilog to C++. Companies like Tesla use it and report speed ups of up to 40 compared to commercial tools. Similarly for vhdl there exists ghdl, which seems pretty feature complete and has an LLVM backend

[q3k]

Right, but these are simulators, while the article is looking for a language to both simulate and synthesize using open source tooling.

Yosys (which AFAIK is still the only non-toy open source synthesis tool) supports a _very_ small subset of SV, and does not support VHDL (at least in the open source version).

[Unklejoe]

> Intel has Chipscope

I think "Chipscope" is a Xilinx thing actually.

[lnsru]

You’re right! It’s Signaltap II.