[q3k]

> I am curious, why System Verilog isn’t mentioned in this article. It is much much better than Verilog and is used in industrial applications.

Probably because it has very limited support in open source tooling, same as VHDL.

[orbifold]

That is not true: Verilator is an excellent tool that compiles a large subset of synthesizable System Verilog to C++. Companies like Tesla use it and report speed ups of up to 40 compared to commercial tools. Similarly for vhdl there exists ghdl, which seems pretty feature complete and has an LLVM backend

[q3k]

Right, but these are simulators, while the article is looking for a language to both simulate and synthesize using open source tooling.

Yosys (which AFAIK is still the only non-toy open source synthesis tool) supports a _very_ small subset of SV, and does not support VHDL (at least in the open source version).