[gsmecher]

It's not quite fair to say the tooling is flat-out awful. Vivado is much better than ISE. The place/route algorithms matured (analytical placement rather than simulated annealing), and the software it's wrapped in grew up (it's now tcl-driven and much more script- and revision-control-friendly.) Vivado was a heroic effort and Xilinx deserves credit for taking software seriously, and getting so much of it right. If you don't believe me, try hiring an FPGA engineer today to work on an ISE project. You'll get an earful.

That said, a solid, open-source, mixed-language simulator with good SystemVerilog and VHDL-2008 support would change my life. Bonus points if I can embed it in C/C++ code a la Verilator. And, while I'm asking, can it simulate encrypted IP too?

This is one of the places where HLS may sideswipe the traditional RTL market: if you can effectively develop FPGA designs in C++, the entire approach to development/testing/integration changes completely. It may sound like a detail, but it touches every single pain point associated with a complex FPGA design.

[jhallenworld]

I'm using Vivado right now. Things I hate about it:

- It's sluggish. The underlying algorithms may be fast (they handle huge designs), but even with an empty design it's sluggish. I'm not sure if this is from the Java or the TCL. On the other handle Altera/Intel Quartus is faster.. (it also uses Java and TCL..)

- I hate TCL. This whole concept of an integrated extension language in a massive tool is terrible. It's the standard way in the EDA world, but it's not good at all. I prefer simpler tools tied together with Makefiles..

- I hate the schematic-like block designs. I just want a single Verilog file that represents the design, no XML. The block designs are difficult to integrate with git.

- I hate projects. They are difficult to integrate with git: you have to export project tcl, then regenerate the project from this checked in file. It's aweful and breaks when the design gets complicated.

- I'm using Zynq Ultrascale+ and I hate eclipse. The EDK is eclipse-based. I just want a command line tool to generate a project from the hardware description so that I never have to open the Eclipse. True, once your hardware is stabilized, you can avoid it (it does generate a Makefile). I've not tried Altera's SoCs, so not sure if better.

That being said, Xilinx did a good job with the BSP software and the Linux support. At least it's better than what we see on some embedded processors (Nvidia, ugh..)

Also I recently ported a design from Zynq (32-bit) to Zynq Ultrascale+ (64-bit). Not bad at all.

[btashton]

You can generate the sdk including the makefiles from the command line. I don't think I have opened Eclipse on my latest project.

They also do have some articles on preparing the projects for git which work OK, but yeah there is a lot more to be done.

I'm not sure how you would replace the tcl scripts with makefiles. Most of them contain functions to wire together not build targets.

[gsmecher]

These are all fair criticisms. Block designs, XML files for project and IP management, and auto-generated .tcl are all bad things. Eclipse sucks.

I understand why vendors ship tools with all of these things. I think (hope?) they're slowly un-bundling more and more of the toolflow so you can avoid them if you want.

[kevin_thibedeau]

FWIW the ISE tooling was all command line driven and could be orchestrated from a makefile and controlled by a VCS. You'd lose some of the graphical convenience to monitor issues and reporting but it can be done.

HLS's problem is how to deal with assumptions about memory access and parallelism. You invariably end up coding to the tool to accommodate the limitations of C in this domain.