| I'm using Vivado right now. Things I hate about it: - It's sluggish. The underlying algorithms may be fast (they handle huge designs), but even with an empty design it's sluggish. I'm not sure if this is from the Java or the TCL. On the other handle Altera/Intel Quartus is faster.. (it also uses Java and TCL..) - I hate TCL. This whole concept of an integrated extension language in a massive tool is terrible. It's the standard way in the EDA world, but it's not good at all. I prefer simpler tools tied together with Makefiles.. - I hate the schematic-like block designs. I just want a single Verilog file that represents the design, no XML. The block designs are difficult to integrate with git. - I hate projects. They are difficult to integrate with git: you have to export project tcl, then regenerate the project from this checked in file. It's aweful and breaks when the design gets complicated. - I'm using Zynq Ultrascale+ and I hate eclipse. The EDK is eclipse-based. I just want a command line tool to generate a project from the hardware description so that I never have to open the Eclipse. True, once your hardware is stabilized, you can avoid it (it does generate a Makefile). I've not tried Altera's SoCs, so not sure if better. That being said, Xilinx did a good job with the BSP software and the Linux support. At least it's better than what we see on some embedded processors (Nvidia, ugh..) Also I recently ported a design from Zynq (32-bit) to Zynq Ultrascale+ (64-bit). Not bad at all. |
They also do have some articles on preparing the projects for git which work OK, but yeah there is a lot more to be done.
I'm not sure how you would replace the tcl scripts with makefiles. Most of them contain functions to wire together not build targets.