[jhayward]

Trillions of cycles isn't that "limited", compared to e.g. Flash.

[baybal2]

FRAM is far from trillions of cycles, more close to billions, which still kills it after ~5-7 years of intense use.

[castratikron]

No, FRAM really is in the trillions of RW cycles.

https://www.cypress.com/file/209146/download

[baybal2]

TI spec for FRAM is 10^10, but in real life you do feel that it's noticeably lower.

[castratikron]

TI micros are overpriced anyways. The NXP RTs are way better bang for the buck.

[naikrovek]

That's more than flash. That's more that an SSD, even, probably.

If you're writing to flash or FeRAM that much it seems to me that You're Doing It Wrong.

[LocalH]

Flash, I'd agree. But with FeRAM, if you're reading, you're writing either way.

[zaarn]

What microcontroller will see continued and "Intense" use of it's internal flash?

The worst I do to mine is to log sensor data in absence of wifi, that's in the order of bits/minute.

[baybal2]

Due to destructive reads, any XIP read ends up in a write. And the most grievous case is when your function code ends up just few bits longer than cache. That means that those few bytes will get hammered, individually, every cycle.

TI's spec for 10^10 endurance is for random writes

[zaarn]

Atleast in the µCs that i used that have flash, program code doesn't sit on the same flash as RAM for these precise reasons. Data flash is separate so this shouldn't be an issue.