[baybal2]

Due to destructive reads, any XIP read ends up in a write. And the most grievous case is when your function code ends up just few bits longer than cache. That means that those few bytes will get hammered, individually, every cycle.

TI's spec for 10^10 endurance is for random writes

[zaarn]

Atleast in the µCs that i used that have flash, program code doesn't sit on the same flash as RAM for these precise reasons. Data flash is separate so this shouldn't be an issue.