Hacker News new | ask | show | jobs
by eebynight 2556 days ago
Is it just me or did it sound like the author was complaining the whole time?

"FPGAs aren't evolved like modern processors with standardized programming models, so we must throw out the current model but I have no idea what is better."

Having worked with FPGAs, I can understand his complaints about the toolchain, they absolutely suck and are mostly closed source. This technology is just like microprocessors in its infantry, its evolving.

FPGAs have made crazy progress in the last decade and are getting to the point where it's now affordable for hobbyists and consumers to work with them instead of merely just aerospace & defense contractors with massive hardware budgets.

The problem with Verilog as an ISA is that it is too far removed from the hardware. The abstraction gap between RTL and FPGA hardware is enormous: it traditionally contains at least synthesis, technology mapping, and place & route—each of which is a complex, slow process. As a result, the compile/edit/run cycle for RTL programming on FPGAs takes hours or days and, worse still, it’s unpredictable: the deep stack of toolchain stages can obscure the way that changes in RTL will affect the design’s performance and energy characteristics.

Yes, RTL varies significantly from the actual hardware of the device (LUTs, Memory, Peripherals, etc..) but from a design standpoint, I don't see anything else that would make more sense to work with. FPGAs are significant BECAUSE of the fact that you get build and design at that level. Let's not forget that ISAs are a higher level abstraction of RTL...

3 comments

If I understand your argument correctly, you are saying that complaining is not justified when FPGAs have made crazy progress. Can you explain why making crazy progress means that we could continue using the same abstractions or that the abstractions ar right?

GPU's made crazy progress but they changed because there was better way to make even crazier progress.

> As a result, the compile/edit/run cycle for RTL programming on FPGAs takes hours or days and, worse still, it’s unpredictable: the deep stack of toolchain stages can obscure the way that changes in RTL will affect the design’s performance and energy characteristics.

That's all true but one should really not forget what FPGA's are intended for in the first place: the design of integrated circuits and hours or days is so much better than months for even the simplest custom IC.

There are a few efforts to modernize the toolchain. Inaccel is making some great efforts like integration with Spark, K8s https://www.inaccel.com/fpgas-goes-serverless-on-kubernetes/

Disclaimer: I am investor in InAccel