[wolf550e]

"cpu" is "core". Almost all phone CPUs are multi-core. The low end of phone (and Raspberry Pi 2 V1.2 and newer) CPUs is quad core ARM Cortex A53, which is a small slow in-order design, similar to the original Intel Pentium from 1995. Older low end phones used the 32bit quad core ARM Cortex-A7. single core ARM11 phones are extinct.

They don't mean multi-socket systems, and I don't see mention of NUMA, which is the interesting case for servers where RAM is connected to some memory controller in a socket and to reach it from a CPU in a different socket you need to do extra hops, so some memory addresses are more distance than others and schedulers should take that into account to achieve good performance.

[tonfa]

And phone CPUs can be more complex than most desktops, afaik big.LITTLE is fairly common (multi core, with different performance / power tradeoffs between the cores).

https://lwn.net/Articles/501501/ has some pointers.

[Twirrim]

big.LITTLE is fascinating, and I'm somewhat curious to see if Apple tries to do something along those lines as it supposedly pushes towards ARM chips in their machines.

Google have added some interesting stuff to Android to help it learn over time if tasks should be allocated to the bigger cores or the lower powered smaller ones, based on all sorts of metrics, and I believe this stuff is making its way upstream. There's certainly some really interesting potential around that.

[wolf550e]

Apple chips are big.LITTLE too, at least since the 2016 A10 in the iPhone7.

https://en.wikichip.org/wiki/apple/ax/a12

https://en.wikichip.org/wiki/apple/ax/a10

https://www.anandtech.com/show/13392/the-iphone-xs-xs-max-re...

[Twirrim]

Sure, I should be clear I was thinking about OSX and laptops/desktops, rather than mobile devices.

[wolf550e]

I was just saying the low end chips have only "little" cores, no "big" cores, but they are still multi-core. AFAIK nobody makes single core Cortex A chips. Single core Cortex M chips are made, but those are really puny.

[ansible]

Hilariously, it is common to see some SoCs, like the i.MX8, have Cortex-A and Cortex-M cores. You can do fun stuff like run different operating systems on them too. They can be used for real-time applications, safety-critical functions, etc..

And by "fun" I mean not-fun, because you've got multiple build processes and releases to manage.

[wolf550e]

But I think that's not used as a multiprocessor, with threads getting scheduling on either (or both) depending on power policy. The embedded cores are, I think, used as separate systems running separate OS that happen to have access to the same DRAM, like a peripheral that can do DMA.

Thinking of running that as a single multiprocessing system I'm reminded of the bug caused by Samsung doing big.LITTLE with cores that have the same instruction set but differently sized cache lines: https://news.ycombinator.com/item?id=12481700

[ansible]

> But I think that's not used as a multiprocessor, with threads getting scheduling on either (or both) depending on power policy. The embedded cores are, I think, used as separate systems running separate OS that happen to have access to the same DRAM, like a peripheral that can do DMA.

Right, I didn't mean to imply otherwise.

[brandmeyer]

There are variations on this theme where the two types of cores are also cache coherent with each other.