[wolf550e]

But I think that's not used as a multiprocessor, with threads getting scheduling on either (or both) depending on power policy. The embedded cores are, I think, used as separate systems running separate OS that happen to have access to the same DRAM, like a peripheral that can do DMA.

Thinking of running that as a single multiprocessing system I'm reminded of the bug caused by Samsung doing big.LITTLE with cores that have the same instruction set but differently sized cache lines: https://news.ycombinator.com/item?id=12481700

[ansible]

> But I think that's not used as a multiprocessor, with threads getting scheduling on either (or both) depending on power policy. The embedded cores are, I think, used as separate systems running separate OS that happen to have access to the same DRAM, like a peripheral that can do DMA.

Right, I didn't mean to imply otherwise.

[brandmeyer]

There are variations on this theme where the two types of cores are also cache coherent with each other.