I would not call ARM a RISC. What is RISC in your opinion? Lack of memory addressing except load and store? Not true for ARMv8.1. Lack of microops? ARM1 (from 1985) has microops.
Reduced set of instructions, and simple encoding of them.
ARM instructions are always 32 bit; this includes NEON. There’re signs ARM developer indeed were trying to minimize their count (e.g. there’s no right shift neon instruction, instead left shift is used with negative shift value).
Thumb instructions can be 16 bit, but still this is way simpler than x86, where a single instruction can be between 8 and 120 bits.
"Simple encoding" doesn't mean its RISC. There are simple encoding instruction sets that are CISC. For example - PDP-10, it has fixed size, simple encoding, but is "classically" known as CISC.
CISC vs RISC for modern CPUs (last 20 or 30 years) doesn't mean anything. Any modern ARM or Intel is partially RISC and a CISC at the same time.
Think this way:
1) modern x86 micro-ops can be viewed as RISC. So x86 is RISC?
I don’t think implementation details are relevant for CISC vs RISC. At least not anymore.
I think it’s a characteristic of CPU’s instruction set.
Not the internal undocumented instructions, but the instructions publically available to programmers.
ARM instructions are always 32 bit; this includes NEON. There’re signs ARM developer indeed were trying to minimize their count (e.g. there’s no right shift neon instruction, instead left shift is used with negative shift value).
Thumb instructions can be 16 bit, but still this is way simpler than x86, where a single instruction can be between 8 and 120 bits.