[mmozeiko]

"Simple encoding" doesn't mean its RISC. There are simple encoding instruction sets that are CISC. For example - PDP-10, it has fixed size, simple encoding, but is "classically" known as CISC.

CISC vs RISC for modern CPUs (last 20 or 30 years) doesn't mean anything. Any modern ARM or Intel is partially RISC and a CISC at the same time.

Think this way:

1) modern x86 micro-ops can be viewed as RISC. So x86 is RISC?

2) ARM1 (from 1985) had an micro-ops, that means user visible opcodes are not reduced enough. So ARM it CISC? http://www.righto.com/2016/02/reverse-engineering-arm1-proce... Not talking even about modern 64-bit arm cores.

[Const-me]

I don’t think implementation details are relevant for CISC vs RISC. At least not anymore. I think it’s a characteristic of CPU’s instruction set. Not the internal undocumented instructions, but the instructions publically available to programmers.

Also, ARM says their CPU designs are based on RISC principles: https://developer.arm.com/products/architecture/cpu-architec...