[nickpsecurity]

For those complaining about price, you might want to look into costs that go into ASIC's. Adapteva has a nice write-up on that with their strategies for getting cost down. Note that it was critical to have a few million with a strategy that their own write-up said couldn't work if priced for consumer market. They'd have to charge more or have ridiculous volume.

http://www.adapteva.com/andreas-blog/a-lean-fabless-semicond...

The HiFive product uses a CPU they developed on 28nm. That's one of most expensive nodes you can use. Depending on if and how they split cost, fabbing those chips could've cost over a million dollars in masks. Low-volume, RISC workstations used to cost five digits each on older nodes. Getting a low-volume CPU on cutting-edge node for a grand is a great improvement. So long as they ship products that work as claimed.

There's been a lot of vaporware in FOSS-type hardware...

[monocasa]

I was under the impression that (albeit as of a year ago or so) 28nm was the cheapest node you could work on. The end of Moore's law is starting to hit the industry and smaller nodes were more expensive per transistor still.

[nickpsecurity]

My prior data said most designs were being done well above 28nm (even 90nm) with mask costs increasing as the feature size got smaller. eASIC even still offers 45nm S-ASIC's (Nextreme-2's) for those who can't afford ASIC's at that node. So, I'd be surprised if 28nm cheaper. If 28nm has gotten that cheap, then I'd love to have references on that to give to CompSci folks I've seen doing semi-open or FOSS designs from 90nm-32nm.

Note: I'm also talking for complex designs like a CPU or SoC instead of Bitcoin-mining primitives or something.

Edit: see my response to wmf as I partly answer thoughts on your other question about volume or eating up costs.

[monocasa]

Ohhhh, ok. I think you're totally right for lowish volume runs like this. My information was in the context of where you have enough volume to amortize the mask cost out.

Maybe SiFive is eating the cost here either with the hope that they can sit at 28nm for a while and treat this chip as gravy train money in the long term? Or maybe they just want 28nm experience for higher volume runs in the future?

[imtringued]

The problem is the lack of IO. If they had at least one SATA port and a PCIe port it would make sense to sell this long term. The only way they could possibly fix this problem is by connecting their chiplink to an external SATA and PCIe controller which means they need to fab another chip. This is going to be expensive so I don't see it happening.

[justinclift]

The board specs mention an FMC interface. Isn't that used (with appropriate module) for PCIe connectivity?

[monocasa]

Or use an FPGA which'll be cheaper than any chip they could fab.

[wmf]

Do those costs somehow not apply to ARM SoCs?

[detaro]

ARM SoCs aren't made in low numbers for just a bunch of dev boards, or when they are made that way it's for the first initial testing runs and not publicly available at actual prices.

All these ARM single-board computers use chips that are produced for other purposes in way larger numbers (some of the Raspberry Pi models might be an exception and actually have a slightly customized design just for them, but I'm not sure about that).

[nickpsecurity]

The rule of thumb is to not do an ASIC unless you're selling at least 100,000 units if you want it cheap per unit. The ARM SoC's that get used in a lot of products probably are selling in really high volume. To illustrate the effect, a product that cost $100,000 to design would break-even at $1 a unit in that volume but $1,000 a unit if only 100 were sold. That's idealized: you generally have to pay for the masks, a wafer per set of chips that fit on one (number varies), absorb/charge the cost of broken chips, IC packaging for the chips, shipping, storage, etc. That's not counting boards, assembly or whatever.

So, selling something in high volume like big-name ARM's gets the prices way down per unit. Getting to high volume is a marketing and product development problem more than a technical one. Good luck on the startup. :) The ecosystem benefits will give ARM-based solutions an advantage there for a while into the future. The RISC-V chips will cost more due to lower volume unless all the heavy costs are absorbed at a loss by whoever builds them. I've recommended Universities or foundations attempt that to get good, FOSS chips started on good nodes with them sold at material, assembly, and distribution cost from there.

OpenPITON is another one with potential since they have prototypes for 32-core, OpenSPARC CPU's at 32nm. Leon3 GPL was an older one in SPARC. J2 (SuperH-style) is a compact one that's about 3 cents a core in 180nm with who knows what performance, energy usage and pricing could be achieved at 28nm-32nm. CHERI, a capability-secure extension of MIPS, could be ported to one to give it a security advantage to secure sales from defense sector. Draper is aiming for that with SAFE architecture (crash-safe.org) added to RISC-V. If wanting max reliability (eg safety-critical), VAMP was a 32-bit DLX CPU formally-verified for correctness that could be done on older node with mods for lock-step, triplicated redundancy, or board-level fault-tolerance.

So, there's possibilities to justify higher prices long enough to recover upfront costs or get them down on simpler designs. The HiFive is a serious core on a relatively-recent node, though. It's not going to be cheap unless selling boatloads. They probably didn't expect this product to sell boatloads, either.

[Taniwha]

don't forget the cost of testing - that adds up, often people do simple testing on the wafer to avoid the cost of packaging bad die, then full testing once packaged - remember a bad chip for a semi manufacturer is a whole bad board for their customers

[imtringued]

Most SBCs are based on SoCs that are pretty much end of life. They have already amortised their costs years ago by selling them in smartphones, tv boxes, tablets.