[nickpsecurity]

My prior data said most designs were being done well above 28nm (even 90nm) with mask costs increasing as the feature size got smaller. eASIC even still offers 45nm S-ASIC's (Nextreme-2's) for those who can't afford ASIC's at that node. So, I'd be surprised if 28nm cheaper. If 28nm has gotten that cheap, then I'd love to have references on that to give to CompSci folks I've seen doing semi-open or FOSS designs from 90nm-32nm.

Note: I'm also talking for complex designs like a CPU or SoC instead of Bitcoin-mining primitives or something.

Edit: see my response to wmf as I partly answer thoughts on your other question about volume or eating up costs.

[monocasa]

Ohhhh, ok. I think you're totally right for lowish volume runs like this. My information was in the context of where you have enough volume to amortize the mask cost out.

Maybe SiFive is eating the cost here either with the hope that they can sit at 28nm for a while and treat this chip as gravy train money in the long term? Or maybe they just want 28nm experience for higher volume runs in the future?

[imtringued]

The problem is the lack of IO. If they had at least one SATA port and a PCIe port it would make sense to sell this long term. The only way they could possibly fix this problem is by connecting their chiplink to an external SATA and PCIe controller which means they need to fab another chip. This is going to be expensive so I don't see it happening.

[justinclift]

The board specs mention an FMC interface. Isn't that used (with appropriate module) for PCIe connectivity?

[monocasa]

Or use an FPGA which'll be cheaper than any chip they could fab.