[vardump]

Pretty cool as a design like this should be able to better preserve old system behavior than what DOSBox etc. can achieve.

Although it seems a bit slow side at 50 MHz, I guess it's not a pipelined design?

Not that original 80186 was pipelined either. :)

[kbenson]

The 80286's I grew up using were between 4 and 12 MHz, depending on which model I was on and whether "Turbo" was enabled.

50 MHz is mid to low end 486 territory clock rate, which if it handles instructions as well (a big if) puts it squarely in the area of a lot of games.

[sehugg]

If it isn't pipelined, then it'll probably be more like a 286 or 386 performance-wise. IIRC, Quake only had a smooth framerate on my 486DX-33 with floating-point support.

[jacobush]

Quake should only have worked well on a Pentium because it could execute float instructions in parallel with CPU instructions, or something. At least Quake was unplayable on my 486DX (don't remember MHz, 66 or below). Even Doom was too slow.

[slededit]

FPGAs run an order of magnitude slower than an ASIC would. Most of this is due to routing delays unless you take great care and do a lot of it semi-manually. On the logic side you can't easily do a lot of the fun stuff like cycle stealing and using latches because the FPGA toolchains don't handle that well.

[mbrumlow]

I don't know much. Just getting into FPGAs my self. But from my understanding you could swap out the crystal for a faster one. Most of the FPGA boards I am looking at only come with a 50mhz clock.

There is some complications around changing the clock. It seems to have to do with the complexity of the hdl you load into the FPGA. Many of the boards shipping with 50mhz crystal can easily do over 100mhz.

[buildbot]

You wouldn’t swap out the crystal, you’d use the internal PLLs to generate whatever clock you want. Much easier!

And you are essentially correct, there is a maximum clock speed for any design, and it has to do with how complex your design is. Essentially, what’s the longest path in your design? Your clock must be slow enough to allow a change to propagate through that path. Pipelining shortens this path by creating registers along it, which are clocked by your clock. When a register is clocked, it stores the value in its input side, and outputs that value on the output side.

[ZenoArrow]

Generally speaking, what determines the "clock speed" for FPGAs is a combination of the design of the FPGA device plus the complexity of the design being implemented on it.

Let's imagine you design a CPU on an FPGA. One way to measure the speed of that design is to look at the speed of the slowest operation of that CPU. The clock needs to be set at the speed at which the slowest (most complex) operation can reliably run at.

[davepage]

Most modern FPGAs have a PLL (or DLL) implementation [0] which can multiply the external clock by some rational number. e.g. 50MHz external crystal clock is multiplied by 5/2 to obtain a 125MHz internal clock.

0. https://www.xilinx.com/support/documentation/user_guides/ug3...

[TickleSteve]

The 80186 won't be able to play many games that you remember... it wasn't really PC compatible.

[anyfoo]

The 80186 was completely compatible to its predecessor. It's just that there weren't many IBM-compatible PCs which featured an 80186.

[burfog]

The core was compatible, but it came with built-in non-standard peripherals. It had a DMA controller, interrupt controller, and timer. None of these were PC compatible.

[int_19h]

This particular one sounds like it has all of these, seeing how the webpage shows it running a bunch of DOS games.

[bitwize]

I think he only duplicated the 80186 core (which itself was a bit different from the 8086 core and had a few more instructions), without adding the peripherals that came on-die on an actual 80186.