[ZenoArrow]

Generally speaking, what determines the "clock speed" for FPGAs is a combination of the design of the FPGA device plus the complexity of the design being implemented on it.

Let's imagine you design a CPU on an FPGA. One way to measure the speed of that design is to look at the speed of the slowest operation of that CPU. The clock needs to be set at the speed at which the slowest (most complex) operation can reliably run at.