IMHO, If you have to floor plan, you're doing it wrong.
You should try to design FPGAs so that they work like software, in that you should be able to run the tools consistently like you would software through a C compiler and not have difficulty with failed timing. If you had to do floor planning to close timing, you are giving up a huge advantage.
I think that really depends upon the application. If you're using an FPGA because you need custom hardware but can't justify the cost of a full ASIC then by all means floor-plan (indeed you may need to to close timing at your desired frequency).
If you're building a soft-core CPU designed for a wide range of FPGAs and you can't make it go without a custom floor-plan then yes you're probably doing it wrong.
That's good in theory, but ... it's not realistic. The compilers are too unstable. I lost a couple days of my life last year because Quartus forgot how to route its multipliers.
But usually you only have to floor plan if you're near the limits of your target FPGA, or if you're using some of its special IP (like say pinning some of DRAMs or PLLs).
Yup or your design is just large. Due to the non-deterministic nature of the compiler guiding it at a high level makes it less likely to choose resources in weird locations. e.g. I roughly map out block ram assignments for some of the top level modules but still give it plenty of wiggle space.
Not only that but you don’t want to have to redo analysis and verification on blocks that have been already mapped, placed and routed. Especially as one does minor bug fixes towards the end of a design. It’s like refusing to use libraries.
You should try to design FPGAs so that they work like software, in that you should be able to run the tools consistently like you would software through a C compiler and not have difficulty with failed timing. If you had to do floor planning to close timing, you are giving up a huge advantage.