[notalaser]

> The best startups are ones that solve a pain point you yourself have experienced.

Aww, yisss. Case in point, EDA and, in particular, hardware description languages and tools. Every discussion I've had with someone trying to get into this has been so cringe-worthy that I'm actively avoiding now. Every self-professed hardware hacker thinks they have the solution that's going to end all this painful Verilog kerfuffle and yet they're so, so far from getting it.

Like the folks who thing the biggest problem with Verilog and VHDL is that they're so alien that it's hard to get software developers productive with them. Lack of electronics knowledge is what prevents most software developers from being productive in Verilog. A "better" language won't help. Paying attention in their Electronics or Systems classes is going to be ten times more helpful than a Scala/Haskell/whatever-is-fashionable hardware description language.

Or the people who think that development tools are what's holding FPGAs back and that FPGAs would be everywhere, were it not for how hard it is to program them. Trying to explain them that FPGAs are pretty slow gets impossibly difficult as soon as the words "Intel" and "softcore" are mentioned.

Not that there aren't a lot of things to improve in FPGA development tools, or in hardware description languages (which is why you see so much work being done on increasingly higher-level synthesis tools). But unless the number of millions of dollars you're willing to invest is not at least half the number of years you've been studying high-speed IC design, chances are you're as far removed from having a serious answer to all these problems as you are removed from being a modest person.

/rant

[throwaway2016a]

Lol. Funny you should say that.

My wife was an Electrical Engineering major and when I started dating her I saw the Verilog and actually tried to improve it. Although my approach was more a better IDE and emulator than reinventing the language.

I didn't get far. The domain knowledge of electronics needed was too much for me to deal with and still do my own coursework.

[gluggymug]

>Lack of electronics knowledge is what prevents most software developers from being productive in Verilog. A "better" language won't help.

I am working in the FPGA industry. I definitely agree with you.

But possibly I am a little too close to the current industry and way we do things. There's new applications around the corner that need innovative ideas. The innocent fresh perspective could be the seed for something. I am sure if any real decent improvements were started by a SW person, the big companies like Intel would be eating it up.

It funny how people on HN were raving about Altera & Intel recently because word on the FPGA street was that Intel weren't happy with the acquisition. Xilinx has had 14nm FPGAs for a long time while Altera's are nowhere to be seen still. Everyone's expectations of a Xeon with Altera FPGA on the same die are years away I am betting.

[planteen]

Agreed. I have worked with FPGAs at multiple companies, both on the logic side and on the software side interfacing with them. Verilog and VHDL are not the problem. The problems I have seen, over and over are:

1. Improper clock domain crossing

2. Improper timing constraints

I have never used ASIC quality verification tools. But to me a free tool from Xilinx/Altera like valgrind or clang sanitizer would be huge for FPGAs.

Or even just a way to "diff" two bitstreams, one that is "bad" and one that is "good" that were from the same source to see what makes the bad FPGA bad would be huge. I mean bad in the sense that some probabilistic/annealing algorithm used during FPGA synthesis on a net with an incorrect timing constraint lead to a FPGA that doesn't work as intended.

I went from logic to doing software. Can't say I miss the FPGA world. Seems so much easier to get software right.

[pjc50]

Heh :) I've been in an EDA startup, done FPGA work, and I even have a tiny corner of silicon on a shipping IC. I have a draft for a "better verilog" sitting in a text file. Verilog and VHDL are stuck in the FORTRAN77 era.

I've no intention of taking it further than that, because the industry is extremely conservative and there's no money in programming languages.

(I agree that the FPGA-silver-bullet people are annoying. And that people need to realise that FPGA is not programming. But perhaps the tools could help a bit more with that.)

[Artlav]

Interesting, i thought the problem was the other way around.

I find Verilog quite intuitive as is, but the tools are rather crude. I.e. until recently Altera's Quartus felt like a hack some students put together in their spare time - missing basic IDE features, interface bugs that get in the way, poor programmer support on Linux and so on.