[planteen]

Agreed. I have worked with FPGAs at multiple companies, both on the logic side and on the software side interfacing with them. Verilog and VHDL are not the problem. The problems I have seen, over and over are:

1. Improper clock domain crossing

2. Improper timing constraints

I have never used ASIC quality verification tools. But to me a free tool from Xilinx/Altera like valgrind or clang sanitizer would be huge for FPGAs.

Or even just a way to "diff" two bitstreams, one that is "bad" and one that is "good" that were from the same source to see what makes the bad FPGA bad would be huge. I mean bad in the sense that some probabilistic/annealing algorithm used during FPGA synthesis on a net with an incorrect timing constraint lead to a FPGA that doesn't work as intended.

I went from logic to doing software. Can't say I miss the FPGA world. Seems so much easier to get software right.