[dragontamer]

Speed isn't the only consideration here. 5x the speed needs 5x the RAM to store it in. But FPGAs will NEVER have as much RAM as a dedicated microcontroller.

Again, you're looking at ~320kBytes on the $25 STM32 microcontroller board, against ~30kBytes on the $25 FPGA board. With 1/10th the RAM, the FPGA will store far less useful data.

The typical Oscilloscope is like 100MHz. Getting a cheap 75MHz logic analyzer is perfectly acceptable. Storing and processing all that data (ie: outputting it to an Ethernet port) start to become the main issues once the speed issue is solved.

In my experience, those small FPGAs run out of room rather quickly too. Throw down something as simple as a Wallace tree multiplier and suddenly half your LUTs are eaten up.

[revelation]

What are you even talking about? FPGAs routinely interface with DDR3 and other "big buckets of memory" should you need them. Try that with your STM32.

[dragontamer]

What price point are we talking about here?

Throw down a single DDR3 Memory chip, and you've already eaten up like half the $25 hardware budget.

http://www.digikey.com/product-detail/en/micron-technology-i...

The "embedded" solution is: buy embedded on-board SRAM when you need it, and if necessary, buy an embedded on-board SRAM memory controller if you need it. Building your own memory-controller out of an FPGA sounds like hell to layout.

Anyway, if we're talking about cheap stuff, DDR3L isn't the technology of note. This is about simpler SDRAM-level stuff, maybe a few MB at a time is sufficient.

----

Furthermore: How many LUTs will your memory controller take up?

http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/I...

According to this, Lattice's DDR3L 16-bit memory controller is 2500 LUTs. The $25 FPGA only has 6300-LUTs, so you've already used up 40% of the chip on just memory-interfacing!

Yeah, you can accomplish a lot with a $600 FPGA with a Million-bajillion-LUTs and embedded cores. But at the $25 price point, FPGAs often run out of room. You don't have many LUTs to work with.

Dollar-for-dollar, a microcontroller will outperform an FPGA in most tasks. That's just the facts. ASIC-implemented memory-controllers and ASIC-implemented large banks of internal SRAM just work better for computer-like tasks.

FPGAs should be used for custom logic that isn't typically handled by a microcontroller / microprocessor. Not memory-controllers and ALUs that already exist in an easily packaged form. There's a reason why high-level FPGAs have embedded ARM cores and embedded memory-controllers in them (alas: such technology is likely out of the reach of cheap $25 FPGAs)

[jhallenworld]

For $90, get this board:

http://www.latticesemi.com/Products/DevelopmentBoardsAndKits...

Includes 45K LUT FPGA with 250KB on-die RAM, DDR3, controller license and PCIe.. Actually this is so cheap I wonder if they are about to discontinue it.

Anyway, I otherwise think the capture the data with the DMA trick is cool. There are a bunch of projects which do the reverse: generate video with SPI output with tricks to make jitter free sync signals.

[zokier]

Here is just a random FPGA board with onboard 32MB SDRAM. All with whopping $17 BOM according to the author:

> Earlier this year, I calculated the part cost of the CAT Board with an HX8K at $17

https://hackaday.io/project/7982-cat-board

[dragontamer]

SDRAM is a simpler kind of RAM and is likely what would be used in the project of the original post.

I seem to have gotten myself sidetracked by the DDR3 comment, but yeah, going to SDRAM is a practical solution

[revelation]

Only 1/3rd for the DDR3 controller? That's a great result, given the remainder of a logic analyzer is.. well let's just say there is not much to it, even with protocol decoding.

The point here is: you can get the DDR3 IP block, put it into your FPGA, and your timing will still work just fine. Which is of course kind of a big deal here. I can't put close to the level of logic in a DDR3 interface in a microcontroller and still have it hit the correct timing; all of that pretty much falls apart at the mention of "pipelining" or "vectored interrupt controller". Try doing protocol decoding on the same microcontroller that does the sampling.

[dragontamer]

Erm, you just buy a microcontroller that supports DDR3 out of the box if you care about large amounts of RAM. There are literally thousands of microcontrollers out there, with a configuration for every single possible task imaginable.

In contrast, you "contact the sales office" of an IP-block of Verilog and read through a ton of FPGA documentation.

I mean, if you really want to just "buy one chip" and do everything with it, be my guest. But honestly, its sometimes easier to just go to a different page in Digikey and buy what you need, instead of trying to build everything you need every time.

[revelation]

I don't think you quite realize what kind of microcontrollers would even come with a DDR3 interface. But if you want to waste away a > 500 MHz chip with sampling GPIO and DMAing that to memory (good luck hitting anything close to what an FPGA could do here, that kind of chip tends to come with multiple levels of caching, pinmuxing, ...) you must have a large BoM and power budget.

[dragontamer]

Point. I think most of the chips I was thinking about are simpler SDRAM controllers.

Nonetheless, I still think that you're grossly underestimating the needs of the FPGA / Logic Analyzer. The product communicates to the PC over USB for instance, performs RAM-level compression and seems to handle some logic-analyzing tasks as well (considering it natively supports I2C, UART, and the like).

EDIT: I think I see where you're coming from now. The next steps then would be licensing issues then. Like whether or not a company could effectively sell the IP-block of the memory-controller and distribute it over the internet (as what has happened in this project).

[analognoise]

This is extremely outdated bad info.