[tonyplee]

Two other factors:

Flash connection protocols (sata, ide) allows much faster evolution independent what's on the other side of interface.

If you have a new flash tech that's 2,3x better in density/speed, you can easily deploy it in current generation of high end server in the next few months.

RAM protocols (DDR2,3,4) must be developed 100% in sync with the CPU vendors. If the major cpu vendors (Intel, AMD, ARM Soc, Qualcomm) decide they don't want your new 2,3x better interface speed/density, you have zero chance to deploy it. It takes years for JEDEC to agree on new memory interface standard. Your new 2,5,10x better tech's deployment is actually depend on your competitors agree to allow it to be the new standard.

Flash can have higher latency as trade off if needed. DDR interface's latency has high impact on the CPU/system benchmark.

[ryao]

CPUs typically support larger DIMM sizes than exist at launch. Having to wait on CPU manufacturers to support larger sizes is probably not an issue. Having an incredibly small market for those larger sizes probably is more of an issue. The Things stored in RAM are replaced all the time. The things stored in flash typically are not replaced, but appended, creating a demand for more.

[peller]

I think more what the parent post was getting at is perhaps better visualized:

For flash storage, the hierarchy looks like this:

CPU -> standardized interface (PCIe, SATA) -> Controller Chip -> NAND

For DRAM, it looks like this: CPU -> DRAM

The DRAM controller is (these days[0]) built directly into the CPU, whereas for flash storage, the NAND controller communicates with the CPU (indirectly) over a standardized interface. So for flash storage, the designers have control over which controller chip they use, and as such can change the NAND technology used at will. They aren't even limited to NAND, if something better comes along. Whereas with RAM, you can't just plug DDR4 into a CPU that only "speaks" DDR3. I think that flexibility is the important distinction.

[0] It used to be that the DRAM controller was on the northbridge, which was a separate chip from the CPU. But for the purposes of performance and power consumption, the tradeoff with flexibility was made (The Athlon 64 was the first [consumer?] CPU to put the memory controller directly on-die, and that was a large part of the reason it crushed the Pentium 4.)

[pixl97]

CPUs may, but getting BIOS support on your particular board may be an issue. I've had a number of boards over the years where I had to wait months for the manufacturer to put out an update to support new DIMM sizes correctly.

[rossjudson]

Make those protocols NVME, PCIe and SATA. Don't think I've seen an IDE flash drive yet ;)

[jamesfmilne]

CompactFlash (CF) is effectively IDE/PATA.