[peller]

I think more what the parent post was getting at is perhaps better visualized:

For flash storage, the hierarchy looks like this:

CPU -> standardized interface (PCIe, SATA) -> Controller Chip -> NAND

For DRAM, it looks like this: CPU -> DRAM

The DRAM controller is (these days[0]) built directly into the CPU, whereas for flash storage, the NAND controller communicates with the CPU (indirectly) over a standardized interface. So for flash storage, the designers have control over which controller chip they use, and as such can change the NAND technology used at will. They aren't even limited to NAND, if something better comes along. Whereas with RAM, you can't just plug DDR4 into a CPU that only "speaks" DDR3. I think that flexibility is the important distinction.

[0] It used to be that the DRAM controller was on the northbridge, which was a separate chip from the CPU. But for the purposes of performance and power consumption, the tradeoff with flexibility was made (The Athlon 64 was the first [consumer?] CPU to put the memory controller directly on-die, and that was a large part of the reason it crushed the Pentium 4.)