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by kc5tja
3461 days ago
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In what way is RISC (a horizontal encoding designed to be efficient to decode) different from a 118-bit uop (a horizontal encoding of microarchitectural to-dos in subsequent pipeline stages)? If you can explain without adding yet another shape-shifting definition of what RISC is, or without pigeon-holing it, that would be awesome. From my perspective, a uOP and a RISC instruction are absolutely identical in intent, which is the point of RISC to begin with: the intent to be efficient to decode. |
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That 118 bit uop is a microarchitectural implementation detail. It has a pedigree dating not just to the VAX but to 1957, to Wilkes' EDSAC.
In what way is this 118 bit uop not microcode? It is not designed for generality. It isn't exposed (other than # of uops in the Intel Optimization Manual or it is Agner Fog). A complex instruction is in fact interpreted just as POLY was on the VAX. It controls a pipeline. It is anything but Reduced.
Calling VLIW and x86 uops RISC doesn't make them RISCs.