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by CalChris
3468 days ago
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A RISC ISA is an ISA. It's an architectural contract which can be implemented many ways. That 118 bit uop is a microarchitectural implementation detail. It has a pedigree dating not just to the VAX but to 1957, to Wilkes' EDSAC. In what way is this 118 bit uop not microcode? It is not designed for generality. It isn't exposed (other than # of uops in the Intel Optimization Manual or it is Agner Fog). A complex instruction is in fact interpreted just as POLY was on the VAX. It controls a pipeline. It is anything but Reduced. Calling VLIW and x86 uops RISC doesn't make them RISCs. |
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