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by Altay- 3539 days ago
Perhaps I'm guilty of falling for marketing definitions, but aren't we already down to 14nm rather than the 20nm the article suggests in the opening paragraph?

>They knew that the laws of physics had set a 5-nanometer threshold on the size of transistor gates among conventional semiconductors, about one-quarter the size of high-end 20-nanometer-gate transistors now on the market.

2 comments

I think 14nm is the current smallest feature size in modern cpus. Like a resolution. A transistor is made up of multiple features.
This is correct. And many foundries will be manufacturing 7nm transistors in 2017-2018. So it seems like this article is a bit incorrect.
When they say that they are manufacturing a 7nm transistor it means the smallest feature is 7nm across. The gate size isn't always the smallest feature of a transistor; it typically is, but not always. And sometimes the larger features can be 4 to 5 times bigger, i.e a drain can be 40~50nm across because it connects to multiple other transistors or is part of a compound transistor. Transistors are inherently analog devices and so feature layout isn't as simple as "I need an XOR gate in this part of the circuit".
14 nm is just a name at this point, as discussed in this public available article:

"Between the ill-defined naming of new process nodes across the entire industry and Intel’s continuing lead in semiconductor manufacturing, Intel likes to point out how their manufacturing nodes compare to foundry competitors such as TSMC and the IBM alliance. Citing 3rd party journal articles for comparison, Intel claims that along with their typical lead in rolling out new nodes, as of the 14nm node they are going to have a multiple generation technical advantage. They expect that their 14nm node will offer significantly smaller feature sizes than competing 14nm nodes, allowing them to maintain consistent logic area scaling at a time when their competitors (i.e. TSMC) cannot." http://www.anandtech.com/show/8367/intels-14nm-technology-in...