[wmf]

So if a RISC cpu takes 10 instructions to do what a CISC can do in 1, it loses any speed advantage if it takes 10x as long to get the next instruction from memory.

99% of the time instructions come from the instruction cache, not from memory. And as jws said, it's not 10:1.

[kjhghjmkedfcv]

Yes and in practice ARM isn't really RISC and x86 isn't really CISC, with VLIW and pipelines and caches it's more complex.

But the original RISC research was in a time when neither CPU clocks nor memory bandwidth was anywhere near physical limits.

It's not the RISC(Apple) is clever and CISC(intel) is a dumb dinosaur - message the article is aiming at.