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by kjhghjmkedfcv
5928 days ago
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Yes and in practice ARM isn't really RISC and x86 isn't really CISC, with VLIW and pipelines and caches it's more complex. But the original RISC research was in a time when neither CPU clocks nor memory bandwidth was anywhere near physical limits. It's not the RISC(Apple) is clever and CISC(intel) is a dumb dinosaur - message the article is aiming at. |
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