[mnw21cam]

The ROM is basically acting as an FPGA. After all, an FPGA is just a load of units of small ROM areas, with the inputs and outputs linked to each other. If all you need to implement your circuit is a single unit, then a small ROM chip is quite sufficient instead.

[adwn]

> The ROM is basically acting as an FPGA.

No, it doesn't; neither from a practical, nor from a theoretical point of view. Theoretically, ROMs are equivalent to the class of pure, total, mathematical functions (i.e., each input value maps to exactly one output value), while FPGAs are equivalent to the class of deterministic finite automata, because they contain internal state.

> After all, an FPGA is just a load of units of small ROM areas, with the inputs and outputs linked to each other.

You're forgetting the memory elements – they're crucial to the functionality of FPGAs.

[duskwuff]

> You're forgetting the memory elements – they're crucial to the functionality of FPGAs.

I'd argue that an even more critical feature of FPGAs is configurable routing. ROMs don't have that either. :)

[adwn]

True. But then again, that's like arguing over which organ is more important – the heart or the lung – when you can't survive without either of them ;-)

[duskwuff]

You can build memory elements - inefficiently, but it's possible - out of recurrent logic. You can't build routing.

Actually, now I wonder whether it'd be possible to build memory out of ROM by looping outputs back to inputs...

[adwn]

> You can't build routing.

You actually don't need configurable (programmable) routing: We can model every synchronous circuit as a Mealy machine [1], therefore we need two functions and a register. Every function can be constructed from a hierarchy of programmable, fixed-size LUTs which are statically connected (for example, you can build a 5-input LUT from three 4-input LUTs). Now you don't need to build routing, it's implicit in the next-state and output functions.

[1] like this: http://electrosofts.com/verilog/mealy.gif