[gluggymug]

Firstly, I commend you on your work.

Second, I looked into your tests directory and from first impressions there's not much there. What is there is kinda messy and not conducive to thorough testing.

If I could make a suggestion: you should look at reusing the work of others. You are in the lucky position where some work has been done for you! There's a massive amount of tests for RISC-V that already exist at https://github.com/riscv/riscv-tests (by weird coincidence someone posted links about this in another thread a few days ago!)

If I were you I would be going through that stuff to try figure out how to get those tests running in my environment. E.g. You have to compile a test and create a mechanism to load the binary into your testbench memory or whatever.

[_chris_]

"E.g. You have to compile a test and create a mechanism to load the binary into your testbench memory or whatever."

God, that's always the hardest part about these things. The core takes you a weekend, but the connection to the outside world takes forever.

[gluggymug]

I think I am one of those who would do it the other way around, from the outside inwards connecting to the outside world first. I already know ALL the I/O for the core is somewhere in the RISC-V design code (exact signal names etc). It has to be in Chisel or something.

I would translate that to VHDL to get my ports. It becomes a stub to build my core-level testbench on. If I can mirror their test environment, I at least have a start point. Maybe I could even reuse their testbench somehow.

Then I'd start duplicating the sub modules and their interconnections in the core. And so on.

Do the tough stuff first then enjoy things getting easier as I go along hopefully!

[inforichland]

Thank you :) Also thanks for the information; I had been wondering if someone had made some more thorough automated tests, I will definitely check those out!