[alain94040]

Happy to provide some quick feedback on your coding style:

Please don't use initial blocks to initialize values, use an always block with reset. That will also solve the issue of having multiple drivers per signal (bad). Also, don't load memories from the RTL, do that from the test bench (using hierarchical references).

  initial begin
	$readmemh({`OLDLAND_ROM_PATH, "decode.hex"}, microcode, 0, 127);
	rd_sel = 4'b0;
	update_rd = 1'b0;
	alu_opc = 5'b0;
	branch_condition = 4'b0;
	alu_op1_ra = 1'b0;
	alu_op1_rb = 1'b0;
	alu_op2_rb = 1'b0;
	mem_load = 1'b0;
	mem_store = 1'b0;
	mem_width = 2'b0;
	pc_plus_4_out = 32'b0;
	instr_class = 2'b0;
	is_call = 1'b0;
	update_flags = 1'b0;
	update_carry = 1'b0;
        cr_sel = 3'b0;
        write_cr = 1'b0;
        spsr = 1'b0;
        is_swi = 1'b0;
	is_rfe = 1'b0;
	i_valid = 1'b0;
	cache_instr = 1'b0;
	exception_start_out = 1'b0;

end

If someone knows of a community like HN that can write great Verilog, let me know.

[smalley]

The closest thing I can think of as far as communities would be the http://www.edaboard.com/ folks (although that's a lot of students) or opencores.org (which is more just general projects).

There are a lot more "news" esk hardware design places as well but I'm assuming you're looking closer to stack overflow/github of HDL rather than the slashdot/reddit of HDL?

If you want HDL best practices any of the resources you can get your hands on from http://www.sutherland-hdl.com/papers.html <-- those folks are excellent

and I would highly recommend this book: http://www.amazon.com/SystemVerilog-Verification-Learning-Te...

[jamieiles]

Thanks for the feedback. With regards to initial blocks, the advantage of using them on an FPGA design is that it's just the initialization value of the registers in the bitstream so doesn't have any real cost, but doing it with a reset would take logic, no? Does that really qualify as multiple drivers?

For the memory loading, I don't know how you'd infer a ROM another way - aren't hierarchical references only supported in simulation/test benches?

[alain94040]

Doesn't your design need to handle reset anyway? If so, then the initial block is redundant. If your design doesn't have a reset, that's highly unusual.

If your target wasn't an FPGA (but an ASIC), the initial block would be completely ignored, so who knows in what state your design would start. FPGAs are nice, they let you specify initial values. Real chips don't. Just put all initial values in your reset clause, in the same always block you assign those registers. Let the FPGA compiler optimize the logic if it can, or infer a mux if it must.