[pjc50]

Verilog in particular leads you into that trap, though. Because you can write conventional sequential-execution programs in it, and usually have to when writing testbenches. The nomenclature of "process" and "task" imply they behave like software - and they do, in the simulator. Then there are the hoops you sometimes have to jump through in order to get the synthesis to behave as you want: "reg" is not always a D-type flip flop, and is mandatory in some places where it doesn't synthesise to one.