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by gluggymug
4055 days ago
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Latches are caught by the synthesis tools generally. Designers usually run a unconstrained synthesis as a matter of course to determine whether they have written junk. As for the other bugs, I look forward to this new paradigm of spotting them early without verification effort. Reasoning about transactions is already how verification works. It is transaction based. UVM is a library of SystemVerilog classes aimed at abstracting the verification to higher levels. Check out:
https://verificationacademy.com/verification-methodology-ref... We build over these classes to create our test benches. |
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