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by makomk 4080 days ago
One nasty little caveat is that Xilinx's tools will not synthesize certain elements, such as state machines, in the way you've written them for performance reasons. Caught me out - I was trying to use an open source design someone else had created with Synplify, and it used a Grey-code state machine to cross between two clock domains. Xilinx's synthesis tool replaced it with a one-hot state machine which was not safe for this purpose and worked for a while then randomly wedged itself. To be fair, the synthesis log did mention this in amongst the huge pile of other messages.