[beeworker]

While this is sort of true, this attitude contributes to the problem another commenter mentioned about how working with FPGAs is like taking a trip to the 70s. There's no reason you can't use a full-fledged programming language like Python to specify your hardware with the strict HDL subset at the RT Level, then use the full language's power to test it off-FPGA, and use all the software tooling around your full language to make the whole experience as pleasant as possible. In fact, that's the approach of MyHDL: http://www.myhdl.org/

[aprdm]

Yup, made an experiment with it -> http://www.eetimes.com/author.asp?doc_id=1323837

I really like MyHDL!