From the pdf walterbell linked to,section "System Overview":
>...two ARM® Cortex-M0 processors are located in separate layers with different functionality as follows:
>The DSP CPU efficiently handles data streaming from the imager (or other sensors), thus is built in 65nm CMOS (Layer 3) with a large 16kB non-retentive SRAM (NRSRAM).
>The CTRL CPU manages the system using an always-on 3kB retentive SRAM (RSRAM) to maintain the stored operating program, and is built in low leakage 180nm CMOS.
For ROM, the CTRL CPU just always keeps its SRAM powered.
I can't seem to find the CPU frequencies, but I would imagine they are very low, as a previous slightly larger version in 2010 had a Cortex M3 working at 1MHz max[1].
>...two ARM® Cortex-M0 processors are located in separate layers with different functionality as follows: >The DSP CPU efficiently handles data streaming from the imager (or other sensors), thus is built in 65nm CMOS (Layer 3) with a large 16kB non-retentive SRAM (NRSRAM). >The CTRL CPU manages the system using an always-on 3kB retentive SRAM (RSRAM) to maintain the stored operating program, and is built in low leakage 180nm CMOS.
For ROM, the CTRL CPU just always keeps its SRAM powered. I can't seem to find the CPU frequencies, but I would imagine they are very low, as a previous slightly larger version in 2010 had a Cortex M3 working at 1MHz max[1].
[1]http://blaauw.eecs.umich.edu/getFile.php?id=394