[kps]

The i860's theoretical throughput was achievable only in very special cases in tight floating point kernels. Most code couldn't possibly perform as well, no matter how smart the compiler.

Intel's sane RISC was the http://en.wikipedia.org/wiki/Intel_i960​, somewhat by accident.

[AlyssaRowan]

And of course, by the time we got to the Pentium Pro - and more or less everything ever since - we ended up with a hybrid pipelined superscalar design which takes advantage of the legacy of support (and, compared to VLIW, tight instruction coding), but as part of the decode pipeline, translates that to RISC µops inside with microcode.

The Transmeta Crusoe was a particularly notable (if not particularly successful) case in point, which brought that layer a little more visibility than most, although in all honestly, was probably mostly well-known for having been Linus Torvalds' employer.

There never was a particularly bright line between RISC and CISC, and it's only gotten blurrier with the decades as the two paradigms stole good ideas from each other.

That's not to say there isn't the occasional throwback, sometimes for a good reason. I've got an adorable little slug of a 'transparent' microprocessor on my desk which I hope sees the light of day sometime (when it actually works, because I've bricked it - first time designer == way too many errata! :P) because it's got some fun ideas for trust, like the host being able to directly read (and verify) all the software it's running.

[spitfire]

i960 was actually a very nice architecture. It had features like proper memory protection, hardware GC support and others that we would absolutely love to have in this day and age.

It was a successor to the Intel iAPX 432 architecture. It also had shades of Burroughs B5000 in it (only RISC). I would love to see a successor to this. Heck I'd like to just have a development board to play with.