[pjmic]

I'm interested to see how a compiler for the Mill CPU would handle such large instruction widths. Whilst it doesn't have the restriction VLIW had of having a fixed instruction width, I'm not entirely convinced we would often see 30+ operations packed in the same instruction.

[jesstaa]

The pipelining talk gives some good examples of where most the the instruction level parallelism comes from. http://millcomputing.com/docs/pipelining/

Most of the rest of the CPU design is really just to enable this.