[scott_wilson46]

I can't help but feel that the VHDL that was written is a bit overly verbose. You could probably write something like:

  i_sm: process(clk, reset)
  begin
    if (reset) then
      state <= DATA_BITS;
    elsif (clk'event and clk = '1') then
      case (state)
        when DATA_BITS => 
          if (data_valid = '1') then
            if (count < 8) then
              count <= count + 1;
            else
              state <= STOP_BIT;
              count <= 0; 
            end if;
          end if;
        when STOP_BITS => 
          if (data_valid = '1') then
            if (count < num_stop_bits) then
              count <= count + 1;
            else
              state <= DATA_BITS;
              count <= 0;
            end if; 
          end if;
       end case
    end if;
  end process i_sm;

which is not too dis-similar from the Cx example (I've missed a few things out like port/signal declerations, just wanted to show the guts of the code). The thing I like about VHDL/Verilog is that its easy to tell the exact port names, what the clk is, the name and type of reset, etc which is useful information for putting the block in the context of an overall system.

[nsiret]

Hi Scott, I'm a co-founder of Synflow. You're right, the VHDL on our website is a bit overly verbose. I will update the website with the right version of the code that day.

And I also agree on your point. This is why we added properties to the language (http://cx-lang.org/documentation/properties) so one can either use the (implicit) default names and types for the clk, reset, etc. or explicit/tweek things for more complex systems.

[scott_wilson46]

Actually another thing I am curious about is how asynchronous clock domains are handled Usually this is something thats quite tricky to model in a HLS tool. Also, how about simulating the interactions between the domains?

[nsiret]

That's a good point Scott. Asynchronous clock domains are indeed complex and it took us time to manage them efficiently. When you need to connect different clock domains with Cx/ngDesign you have to synchronize the various tasks with specific components (e.g. SynchronizerMux) http://cx-lang.org/documentation/instantiation/stdlib. Simulating the interactions between the domains is not yet supported by our simulator. We will develop this feature when people will request it. And you know, we're a startup so we still have plenty of R&D to do :-)

[scott_wilson46]

I think if you can crack the modelling and simulation of asynchronous clock domains then I suspect you will have something that the other HLS solutions don't have at the moment that would be an incredibly useful feature. Design with async clocks is difficult and I have seen loads of bugs with these interfaces (including bugs found in the field for chips that were release many years previously).

[FraaJad]

That Ada roots doe.