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by kubov
4216 days ago
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Verilator[0] can compile Verilog (which, in my opinion, is more friendly than VHDL) to C++ classes code. This is great tool for someone who don't want to spend money on hardware or use vendor specific tools. After compiling top-level module to C++ class, we can use it in code as a regular object. [0] http://www.veripool.org/wiki/verilator |
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