[_chris_]

Hi, are you talking about the Sodor cores? I wrote those and wouldn't mind answering any questions about RISC-V or Chisel.

Regarding Sodor, they're designed to be instructional (we use them on our undergrads at Berkeley) and open for anybody with a C++ compiler so they can learn about Chisel and RISC-V. I pushed them through synthesis once just for kicks, but I didn't work on making them FPGA-ready. Chisel will give you the Verilog of the core, but you'd still need to write a test-harness that's specific to your FPGA.

The RISC-V user manual lists some of our existing RISC-V silicon implementations (8 so far, listed in Section 19.2), whose RTL aren't (yet) open-source.

[cjdrake]

Yes, that's what I was talking about. Dave Patterson was giving a talk in Portland about three years ago on heterogeneous computing, and he mentioned Chisel. And now it seems to be relatively mature. I am happy to see innovation in both the HDL and uArch space.

[trsohmers]

Hey, I've been interested in RISC-V and Chisel, and am a bay area local (Live in Oakland)... what is the best way to get in contact with you and others at UCB?

[_chris_]

Hmmm, I actually have no idea!

Chisel has a google group that you can post any comments or questions you have (chisel.eecs.berkeley.edu). If you wait a week, we should have something similar up at (riscv.org) too.

Chisel has an occasional "boot-camp" where you can come and learn how to use it, and RISC-V will have something similar too I believe in January.