[mjn]

They discuss their reasoning briefly in the manual [1, p. 3]:

We are far from the first to contemplate an open ISA design suitable for hardware implementation. We also considered other existing open ISA designs, of which the closest to our goals was the OpenRISC architecture. We decided against adopting the OpenRISC ISA for several technical reasons:

-- OpenRISC has condition codes and branch delay slots, which complicate higher performance implementations.

-- OpenRISC uses a fixed 32-bit encoding and 16-bit immediates, which precludes a denser instruction encoding and limits space for later expansion of the ISA.

-- OpenRISC does not support the 2008 revision to the IEEE 754 floating-point standard.

-- The OpenRISC 64-bit design had not been completed when we began.

[1] http://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-54...