Honestly, I'm still on the new-ish end of FPGA design (a year or so), so I'm probably not qualified to answer the first one, but I'd have to guess probably not much faster? A fully pipelined CPU could theoretically achieve the maximum clock rate that a given FPGA family could support (i.e. not more than 1 level of logic b/w flops). Actually, yes you could write your own BIOS in some HDL; there are several FPGA dev board that are "USB sticks." See [1] and [2].